Publications

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

LIST OF PUBLICATIONS

1. Published papers in journals by Staff members.

S.No Year of Publish Title Name of the journal Name of the authors ISSN No. Page Nos

2014 – 2015

1 Aug 2014 Multi bit error detection and Correction architecture for motion estimation in video coding systems IJESRT Ms.K.Padamaja Devi 2277-9655 Scientific Journal Impact Factor:3.449Impact Factor:1.852

Pg Nos:505-510

2 Aug 2014 Dynamic Low Density Parity Check Codes For Fault Tolerance On FPGA board in memory applications  IJEVS Ms.P.Gayatri 2349 8129 Vol:3,Issue 8Pg Nos:1-10
3 Sept 2014 Design and Analysis on Single bit to Multi Flip Flop IJSETR Ms.K.Sudha Rani 2319-8885 Vol:3,Issue 24Pg Nos:4918-4922
4 Sept 2014 Designing of BISR technique for multi block memory along resource sharing algorithm IJVDCS Ms.K.Padamaja Devi 2322-0929 Vol:2,Issue 6Pg Nos:0436-0439
5 Sept 2014 FPGA Implementation Of Efficient Modified Booth Encoder Multiplier for Signed and Unsigned numbers IJRAET Mr.A.Vikas Vol:2,Issue 1 
6 Oct 2014 Development Of verification environment for SPI using OVM IJSETR Ms.K.Padamaja Devi 2319-8885 Vol:3,Issue 29Pg Nos:5891-5895
7 Oct 2014 High Throughput Low Area and Low power distributed arithmetic formation for adaptive FIR Filter  IJVDCS Ms.K.Joshna 2322-0929 Vol:2,Issue 7Pg Nos:0445-0449
8 Oct 2014 Design of Dual dynamic node hybrid flip flop with embedded logic design  IJVDCS Mr.D.Sudhakar 2322-0929 Vol:2,Issue 7Pg Nos:0549-0554
9 Oct 2014 A Fixed hardware structure used for built in generation of functional broad side tests  IJRAET Ms.P.Venkata Lavanya Vol:3,Issue 3Pg Nos:08-12

 

10 Oct 2014 Design of high speed multiplierusing multi operand adder trees

 

IJRAET Mr.A.Theja Vol:3,Issue 4
11 Nov 2014 Implementation of Scientific Calculator UsingCORDIC Algorithm on FPGA YUVA ENGINEERS B.SwapnaS.Sai Sree Andal 2320-3706  

Volume No: 3 Issue No: 12

 

2013 – 14

1 July 2013 FPGA Modeling of neuron for future artificial intelligence applications IJCER  Ms.A. Sai Sree 2250-3005 Vol:3,Issue 7 
2 July 2013 High Speed Signed Multiplier for Digital signal processing application IJSETR Ms.K.Padmaja Devi & T.Ganga Bhavani 2319-8885 Pg Nos:546-551
3 Aug 2013 Various power dissipation mechanisms and leakage current reduction techniques in deep submicron technology IJSEAT Mr.D. Sudhakar 2321-6905 Vol:1,Issue 3 
4 July 2013 Complex test pattern generation for high speed fault diagnosis in Embedded SRAM IJMER Mr.S.V.V Satyanarayana 2249-6645 Vol:3,Issue 4 
5 Aug 2013 Random verification of five port network router using advanced EDA tools

 

IJSETR Mr. D. Nageshwar Rao 2319-8885 Vol:2,Issue 8Pg Nos:733-739
6 Aug 2013 Design and testing of prefix adder for high speed application by using Verilog HDL IJCER Ms.P. Venkata Lavanya
7 Aug 2013 Design and Implementation Of Inverse Fast Fourier Transform for OFDM IJSEA Mr.D. Sudhakar 2319-7560 Vol:2,Issue 7Pg Nos:155-158

 

8 Aug 2013 Design of AHB arbiter with effective arbitration logic for DMA controller in AMBA bus IJSETR Ms.Y.Priyanka 2319-8885 Vol:2,Issue 08Pg Nos:769-772

 

9 Aug 2013 Hardware efficient Exon prediction in genome with frequency analysis on FPGA IJSETR Mr.G.Venkata Subba Rao 2319-8885 Vol:2,Issue 08Pg Nos:700-708

 

10 Sept 2013 FPGA implementation of secure hash algorithm (SHA-1)using HDL IJSETR Ms.Y.Priyanka 2319-8885 Vol:2,Issue 11Pg Nos:1167-1170

 

 

11 Sept 2013 Crypto Instruction –Aware RISC Processor IJSETR Mr.K.Rama Krishna Reddy 2319-8885 Vol:2,Issue 11Pg Nos:1105-1110
12 Sept 2013 A Novel Approach for Parallel CRC generation for high speed application IJSETR Ms.K.Sudha Rani 2319-8885 Vol:2,Issue 11Pg Nos:1150-1154

 

 

13 Sept 2013 FPGA implementation Of the Hummingbird Cryptographic Algorithm IJSETR Ms.K.Padmaja Devi 2319-8885 Vol:2,Issue 11Pg Nos:1127-1132

 

14 Sept 2013 A Technique for Test Coverage Closure using Gold Mine IJSETR Mr. D. Nageshwar Rao 2319-8885 Vol:2,Issue 11Pg Nos:1177-1194

 

15 March, 2014 A Faster Carry Save Adder in Radix-8 Both Encoder Multiplier IJTES Ms. K. chandana Reddy 2320-8007 
16 March, 2014 A Fast Locking Analog PLL with De-skew Buffer IJTES Ms. P. Sridevi 2320-8007 
17 May-Jun 2014 Power Efficient Sucessive approximation registers IOSR-JVSP Ms.G.Anitha Choudary eISSn No:2319-4200;     pISSN:2319/4197 Vol:4,Issue3,

Pg Nos:1-7

18 June 2014 Design and Implementation Of Online BIST for different word sizes of memories IJSETR Ms.K.Padamaja Devi 2319-8885 Vol:3,Issue132858-2963
19 June 2014 Design and Performance Analysis of CSLA and CLAA for 32bit Unsigned Multiplier using VerilogHDL IJPRES Mr.B.Amarnath Vol:2,Issue3,

 

2012 – 13

1 May 2011 Enhancement of throughput for multi-hop WPANs by using UWB OFDM physical layer IJCSIS Dr.K.Chenna kesava Reddy 1947-5500 Vol:9,Issue 5Pg Nos:119-124

 

2 July2011 Dynamic approach to improve quality of service in advanced wireless networks IJSR Dr.K.Chenna kesava Reddy
3 Oct 2011 QoS Based Adaptive Admission Controller for Next Generation Wireless Networks IJCTE Dr.K.Chenna kesava Reddy Vol:3,Issue 5Pg Nos:684-689

 

2. Published papers in conferences by the staff members.

S.No Title of the conferences Year Title of the paper National/International Name of the organization Name of the authors Page Nos
1 Innovations in Electronics and Communication Engineering 2014 Design and Analysis of Chebyshev LP-SC Filter International Guru Nanak Institutions Dr.D.Nageshwar Rao 88
2 National Congress on Communications & Computer Aided Electronic Systems 2012 Design Of Data Link Layer 7 MAC layer for CAN using VerilogHDL National Chaitanya Bharathi Institute Of Technology Ms.K.Joshna & Ms. G.Anitha
3 National Conference on Emerging Trends in Electronics & Communication 2010 Design & development Of Microstrip Patch Antenna Array for Wireless Communication Systems National St.Ann’s College Of Engineering & Technology Mr.K.V.Ramprasad
4 International Conference on Control ,Communication and Power Engineering 2010 Application Of Gabor Wavelet for Analysis of Partial Discharge Signal in High Voltage Power Equipment International Association Of Computer Electronics & Electrical Engineers (ACEE) Mr.K.V Ram Prasad
5 National Conference on Applications Of Analog & Digital Devices ECEAADD10 2010 Context Based Modeling For Arial Image Compression National Dr.MGR Educational & Research Institute Ms.K.Sudha Rani
6 National Conference on Applications Of Analog & Digital Devices ECEAADD10 2010 Integrating Logic Analyzer functionality into VHDL designs National Dr.MGR Educational & Research Institute Ms.S.Adilakshmi